JTAG ProVision software suite is used to generate boundary-scan tests and in-system programming applications for assembled PCBs and systems. This professional development tool is fully automated and supports the import of design data from over 30 different EDA and CAM systems. Other key data inputs are JTAG device BSDL models and a large, well-maintained model library describing thousands of non-JTAG devices. All applications can be optimized, validated and run within the ProVision environment prior to delivery of the finished test sequences to the manufacturing and/or testing facility.
JTAG ProVision's development features are tightly integrated with JTAG Technologies’ advanced test analysis tools – Boundary-Scan Diagnostics and JTAG Visualizer. These tools can be used to rapidly assess the thoroughness of the test during development and to make improvements prior to release.
JTAG ProVision, designed for single PCB or system testing, is the most complete boundary-scan applications development tool available today. ProVision supports structural testing of scan path infrastructures, interconnects, IEEE 1149.6 standard interconnects, memory clusters, digital logic clusters and mixed signal clusters. With ProVision you can also prepare programming applications for CPLDs, FPGAs serial PROMs, I2C & SPI devices, NANDFlash etc.. Overall fault coverage can be assessed using the built in coverage examiner tool and the results exported to HTML and CSV formats.
JTAG ProVision is subject to a continuous improvement cycle. New features and device models are introduced on a regular basis.
JTAG ProVision is delivered with over 8.000 models for non boundary scan devices. JTAG Provision currently supports devices from most semiconductor vendors. If however any devices are not supported yet, customer should simply inform JTAG and model library will be updated.
While many ICs are equipped with a JTAG (IEEE Std. 1149.1) boundary-scan register (BSR), a significant number of microprocessors and DSPs can be found with deficient or even non-existent BSRs. CoreCommander Micro uses the on-chip debug mode of processors to access ports and embedded peripheral controllers to promote 'kernel-centric' testing. Similarly, in the case of today’s Field Programmable Gate Arrays (FPGAs) test engineers can 'bridge' from the JTAG interface to the resources of the gate array itself. CoreCommander FPGA product implements a translator interface that allows JTAG hardware to control embedded IP cores via a variety of bus interfaces (e.g. Wishbone Avalon etc.).
CoreCommander micro routines can be used to boost test coverage in applications that have only a small amount or even no IEEE 1149.1 (conventional boundary-scan) test access options. By taking hold directly of the target processor's core the user can write to or read from configuration registers and internal or external memory spaces.
CoreCommander FPGA works by leveraging existing IP that might form part of the configured function of the device. Elements such as DDR memory controllers can now be 'commanded' via JTAG access through a translator block and bus systems like Avalon and Wishbone.
- JTAG control of processors, and FPGAs via core debug access or embedded logic
- Overcomes deficiencies in boundary-scan registers
- Works with devices not compliant to IEEE 1149.x
- Most popular processor cores & FPGAs supported
- Code compatible with Python for test scripting
- Low-cost compared to other solutions
- Supported by JTAG Technologies, JTAG Live and FTDI based controllers/interfaces
- Simple to use interactive GUI to perform core writes/reads
- Processor functions include 'EnterDebug', 'ExitDebug', 'LoadMemory', 'SaveMemory', 'WritePC', 'ReadPC'
- FPGA users benefit from IP access via standard busses Avalon, AMBA, CoreConnect and Wishbone
- Works in tandem with JFT- Python JTAG/boundary-scan routines.
